中文标题#
一種適用於低端 FPGA 的魯棒開源脈衝神經網絡框架
英文标题#
A Robust, Open-Source Framework for Spiking Neural Networks on Low-End FPGAs
中文摘要#
隨著傳統神經網絡對計算能力的需求顯著增加，脈衝神經網絡（SNNs）已成為應對日益耗電的神經網絡的潛在解決方案。 通過操作由神經元發出的 0/1 脈衝而不是算術乘加運算，SNNs 在時間和空間上傳播信息，從而實現更高效的計算能力。 為此，已經開發了許多用於加速和模擬 SNNs 的架構，包括 Loihi、TrueNorth 和 SpiNNaker。 然而，這些芯片對更廣泛的社區來說大多難以獲得。 現場可編程門陣列（FPGAs）已被探索作為類腦和非類腦硬件之間的中間方案，但許多提出的架構需要昂貴的高端 FPGAs 或針對單一的 SNN 拓撲結構。 本文提出了一種框架，包括一個穩健的 SNN 加速架構和一個基於 Pytorch 的 SNN 模型編譯器。 該框架針對任何到任何和 / 或全連接的 SNN，FPGA 架構具有一種突觸陣列，可以在 SNN 中進行鋪排以傳播脈衝。 該架構針對低端 FPGAs，並且只需要很少的資源（6358 LUT，40.5 BRAM）。 該框架在低端 Xilinx Artix-7 FPGA 上以 100 MHz 運行，識別 MNIST 數字的速度具有競爭力（0.52 ms/img）。 進一步的實驗還表明，在玩具問題上能夠準確地模擬手動編寫的任何到任何的脈衝神經網絡。 所有代碼和設置說明均可在https://github.com/im-afan/snn-fpga\}\{\texttt {https://github.com/im-afan/snn-fpga.
英文摘要#
As the demand for compute power in traditional neural networks has increased significantly, spiking neural networks (SNNs) have emerged as a potential solution to increasingly power-hungry neural networks. By operating on 0/1 spikes emitted by neurons instead of arithmetic multiply-and-accumulate operations, SNNs propagate information temporally and spatially, allowing for more efficient compute power. To this end, many architectures for accelerating and simulating SNNs have been developed, including Loihi, TrueNorth, and SpiNNaker. However, these chips are largely inaccessible to the wider community. Field programmable gate arrays (FPGAs) have been explored to serve as a middle ground between neuromorphic and non-neuromorphic hardware, but many proposed architectures require expensive high-end FPGAs or target a single SNN topology. This paper presents a framework consisting of a robust SNN acceleration architecture and a Pytorch-based SNN model compiler. Targeting any-to-any and/or fully connected SNNs, the FPGA architecture features a synaptic array that tiles across the SNN to propagate spikes. The architecture targets low-end FPGAs and requires very little (6358 LUT, 40.5 BRAM) resources. The framework, tested on a low-end Xilinx Artix-7 FPGA at 100 MHz, achieves competitive speed in recognizing MNIST digits (0.52 ms/img). Further experiments also show accurate simulation of hand coded any-to-any spiking neural networks on toy problems. All code and setup instructions are available at https://github.com/im-afan/snn-fpga}{\texttt{https://github.com/im-afan/snn-fpga.
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